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Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita. Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA. pages 176-181, IEEE Computer Society, 2002. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS CircuitsKazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita. delta 2002: 92-98 [doi]
The following publications are possibly variants of this publication: