A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs

Abhishek Shrivastava, Amandeep Kaur, Mukul Sarkar. A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 111-112, IEEE, 2017. [doi]

@inproceedings{ShrivastavaKS17,
  title = {A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs},
  author = {Abhishek Shrivastava and Amandeep Kaur and Mukul Sarkar},
  year = {2017},
  doi = {10.1109/ISOCC.2017.8368794},
  url = {https://doi.org/10.1109/ISOCC.2017.8368794},
  researchr = {https://researchr.org/publication/ShrivastavaKS17},
  cites = {0},
  citedby = {0},
  pages = {111-112},
  booktitle = {International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-2285-8},
}