Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman. Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Trans. VLSI Syst., 24(10):3080-3093, 2016. [doi]
@article{SitikLTS16,
title = {Design Methodology for Voltage-Scaled Clock Distribution Networks},
author = {Can Sitik and Weicheng Liu and Baris Taskin and Emre Salman},
year = {2016},
doi = {10.1109/TVLSI.2016.2539926},
url = {http://dx.doi.org/10.1109/TVLSI.2016.2539926},
researchr = {https://researchr.org/publication/SitikLTS16},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {24},
number = {10},
pages = {3080-3093},
}