Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation

Senthil Sivakumar, S. P. Joy Vasantha Rani. Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation. Journal of Circuits, Systems, and Computers, 28(3):1950042, 2019. [doi]

Authors

Senthil Sivakumar

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S. P. Joy Vasantha Rani

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