A post-processing methodology to improve the automatic design of CMOS gates at layout-level

Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa. A post-processing methodology to improve the automatic design of CMOS gates at layout-level. In 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017. pages 42-45, IEEE, 2017. [doi]

@inproceedings{SmaniottoZCSMMR17-0,
  title = {A post-processing methodology to improve the automatic design of CMOS gates at layout-level},
  author = {Gustavo H. Smaniotto and Regis Zanandrea and Maicon Schneider Cardoso and Renato Souza de Souza and Matheus T. Moreira and Felipe S. Marques and Leomar S. da Rosa},
  year = {2017},
  doi = {10.1109/ICECS.2017.8292073},
  url = {https://doi.org/10.1109/ICECS.2017.8292073},
  researchr = {https://researchr.org/publication/SmaniottoZCSMMR17-0},
  cites = {0},
  citedby = {0},
  pages = {42-45},
  booktitle = {24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-1911-7},
}