Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi. 2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. J. Solid-State Circuits, 44(1):174-185, 2009. [doi]
@article{SomasekharYALKH09,
title = {2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology},
author = {Dinesh Somasekhar and Yibin Ye and Paolo A. Aseron and Shih-Lien Lu and Muhammad M. Khellah and Jason Howard and Gregory Ruhl and Tanay Karnik and Shekhar Borkar and Vivek K. De and Ali Keshavarzi},
year = {2009},
doi = {10.1109/JSSC.2008.2007155},
url = {https://doi.org/10.1109/JSSC.2008.2007155},
researchr = {https://researchr.org/publication/SomasekharYALKH09},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {44},
number = {1},
pages = {174-185},
}