K. Sridharan, T. K. Priya. A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations. IEEE Transactions on Industrial Electronics, 54(3):1800-1804, 2007. [doi]
@article{SridharanP07,
title = {A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations},
author = {K. Sridharan and T. K. Priya},
year = {2007},
doi = {10.1109/TIE.2007.894726},
url = {http://dx.doi.org/10.1109/TIE.2007.894726},
researchr = {https://researchr.org/publication/SridharanP07},
cites = {0},
citedby = {0},
journal = {IEEE Transactions on Industrial Electronics},
volume = {54},
number = {3},
pages = {1800-1804},
}