A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations

K. Sridharan, T. K. Priya. A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations. IEEE Transactions on Industrial Electronics, 54(3):1800-1804, 2007. [doi]

Abstract

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