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K. Sridharan, T. K. Priya. A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations. IEEE Transactions on Industrial Electronics, 54(3):1800-1804, 2007. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA ImplementationK. Sridharan, T. K. Priya. tie, 52(4):1185-1187, 2005. [doi]
The following publications are possibly variants of this publication: