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V. Srinivasan, S. Govindarajan, R. Vemuri. Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. IEEE Trans. VLSI Syst., 9(1):140-158, 2001. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA ArchitecturesVinoo Srinivasan, Ranga Vemuri. fccm 1999: 272 [doi] Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA ArchitecturesVinoo Srinivasan, Ranga Vemuri. fpga 1999: 253 [doi]
The following publications are possibly variants of this publication: