Hongbin Sun, Chuanyin Liu, Nanning Zheng, Tai Min, Tong Zhang. Design techniques to improve the device write margin for MRAM-based cache memory. In David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens, editors, Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. pages 97-102, ACM, 2011. [doi]
@inproceedings{SunLZMZ11,
title = {Design techniques to improve the device write margin for MRAM-based cache memory},
author = {Hongbin Sun and Chuanyin Liu and Nanning Zheng and Tai Min and Tong Zhang},
year = {2011},
doi = {10.1145/1973009.1973030},
url = {http://doi.acm.org/10.1145/1973009.1973030},
tags = {rule-based, caching, design},
researchr = {https://researchr.org/publication/SunLZMZ11},
cites = {0},
citedby = {0},
pages = {97-102},
booktitle = {Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011},
editor = {David Atienza and Yuan Xie and José L. Ayala and Ken S. Stevens},
publisher = {ACM},
isbn = {978-1-4503-0667-6},
}