XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu. XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. In 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018. pages 1423-1428, IEEE, 2018. [doi]

@inproceedings{SunYPLSY18,
  title = {XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks},
  author = {Xiaoyu Sun and Shihui Yin and Xiaochen Peng and Rui Liu and Jae-sun Seo and Shimeng Yu},
  year = {2018},
  doi = {10.23919/DATE.2018.8342235},
  url = {https://doi.org/10.23919/DATE.2018.8342235},
  researchr = {https://researchr.org/publication/SunYPLSY18},
  cites = {0},
  citedby = {0},
  pages = {1423-1428},
  booktitle = {2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018},
  publisher = {IEEE},
  isbn = {978-3-9819263-0-9},
}