Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas. An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. In 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017. pages 116-121, IEEE, 2017. [doi]
@inproceedings{SwornaHBJB17,
title = {An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem},
author = {Zarrin Tasnim Sworna and Mubin Ul Haque and Hafiz Md. Hasan Babu and Lafifa Jamal and Ashis Kumer Biswas},
year = {2017},
doi = {10.1109/ISVLSI.2017.29},
url = {https://doi.org/10.1109/ISVLSI.2017.29},
researchr = {https://researchr.org/publication/SwornaHBJB17},
cites = {0},
citedby = {0},
pages = {116-121},
booktitle = {2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017},
publisher = {IEEE},
isbn = {978-1-5090-6762-6},
}