Multi-Level Circuit Clustering for Delay Minimization - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Cliff C. N. Sze, Ting-Chi Wang. Multi-Level Circuit Clustering for Delay Minimization. In IWLS. pages 227-232, 2002.

The following publications are possibly variants of this publication:

Multilevel circuit clustering for delay minimizationCliff C. N. Sze, Ting-Chi Wang, Li-C. Wang. tcad, 23(7):1073-1085, 2004. [doi]

Optimal circuit clustering for delay minimization under a more general delay modelCliff C. N. Sze, Ting-Chi Wang. tcad, 22(5):646-651, 2003. [doi]

Performance-driven multi-level clustering for combinational circuitsChin-Ngai Sze, Ting-Chi Wang. aspdac 2003: 729-740 [doi]

runs on WebDSL