A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits - researchr publication authors

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Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga. A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. In 6th Asian Test Symposium (ATS 97), 17-18 November 1997, Akita, Japan. pages 320-325, IEEE Computer Society, 1997. [doi]

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