A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits

Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga. A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. In 6th Asian Test Symposium (ATS 97), 17-18 November 1997, Akita, Japan. pages 320-325, IEEE Computer Society, 1997. [doi]

@inproceedings{TakahashiBTM97,
  title = {A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits},
  author = {Hiroshi Takahashi and Kwame Osei Boateng and Yuzo Takamatsu and Toshiyuki Matsunaga},
  year = {1997},
  url = {http://csdl.computer.org/comp/proceedings/ats/1997/8209/00/82090320abs.htm},
  tags = {testing},
  researchr = {https://researchr.org/publication/TakahashiBTM97},
  cites = {0},
  citedby = {0},
  pages = {320-325},
  booktitle = {6th Asian Test Symposium (ATS  97), 17-18 November 1997, Akita, Japan},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-8209-4},
}