Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh. A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. J. Solid-State Circuits, 36(11):1721-1727, 2001. [doi]
@article{TakahashiSTNFMM01,
title = {A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse},
author = {Tsugio Takahashi and Tomonori Sekiguchi and Riichiro Takemura and Seiji Narui and Hiroki Fujisawa and Shinichi Miyatake and Makoto Morino and Koji Arai and Satoru Yamada and Shoji Shukuri and Masayuki Nakamura and Yoshitaka Tadaki and Kazuhiko Kajigaya and Katsutaka Kimura and Kiyoo Itoh},
year = {2001},
doi = {10.1109/4.962294},
url = {https://doi.org/10.1109/4.962294},
researchr = {https://researchr.org/publication/TakahashiSTNFMM01},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {36},
number = {11},
pages = {1721-1727},
}