A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider - researchr publication

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Yonghui Tang, Randall L. Geiger. A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 256-259, IEEE, 2001. [doi]

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