A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques - researchr publication

researchr

You are not signed in
Sign in
Sign up

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto. A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. J. Solid-State Circuits, 44(3):824-834, 2009. [doi]

Abstract is missing.

runs on WebDSL