A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

Che-Wei Tien, Shen-Iuan Liu. A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization. IEEE Trans. on Circuits and Systems, 65-I(6):1830-1839, 2018. [doi]

@article{TienL18,
  title = {A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization},
  author = {Che-Wei Tien and Shen-Iuan Liu},
  year = {2018},
  doi = {10.1109/TCSI.2017.2769721},
  url = {https://doi.org/10.1109/TCSI.2017.2769721},
  researchr = {https://researchr.org/publication/TienL18},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {65-I},
  number = {6},
  pages = {1830-1839},
}