The following publications are possibly variants of this publication:
- 19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellationChe-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu. isscc 2016: 332-333 [doi]
- A Digital Phase-Locked Loop With Background Supply Noise CancellationYen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu. vlsi-dat 2021: 1-4 [doi]
- A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity SuppressionShih-Yuan Kao, Shen-Iuan Liu. tvlsi, 19(4):592-602, 2011. [doi]
- A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled OscillatorJen-Chieh Liu, Yu-Ping Li. access, 9:39717-39726, 2021. [doi]
- A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply RegulatorKuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang. tcas, 59-II(12):888-892, 2012. [doi]