Abstract is missing.
- A Digital Phase-Locked Loop With Background Supply Noise CancellationYen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu. 1-4 [doi]
- Design of 2D Systolic Array Accelerator for Quantized Convolutional Neural NetworksChia-Ning Liu, Yu-An Lai, Chih-Hung Kuo, Shi-An Zhan. 1-4 [doi]
- Chip Performance Prediction Using Machine Learning TechniquesMin-Yan Su, Wei-Chen Lin, Yen-Ting Kuo, Chien-Mo James Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh. 1-4 [doi]
- A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection TechniqueLih-Yih Chiou, Jing-Yu Huang, Chi-Kuan Li, Chen-Chung Tsai. 1-4 [doi]
- A Reconfigurable In-SRAM Computing Architecture for DCNN ApplicationsYu-Hsien Lin, Chi Liu, Chia-Lin Hu, Kang-Yu Chang, Jia-yin Chen, Shyh-Jye Jou. 1-2 [doi]
- Embedded Bearing Fault Detection Platform Design for the Drivetrain System in the Future Industry 4.0 EraKun-Chih Jimmy Chen, Jing-Wen Liang, Yueh-Chi Yang, Hsiang-Ling Tai, Jo-Chiao Ku, Jui-Cheng Wang. 1-4 [doi]
- A 677-μW 90-dB DR 16-kHz BW Incremental ΔΣ ADC for Sensor InterfacesChia-Wei Kao, Che-Wei Hsu, Jia-Sheng Huang, Yu-Cheng Huang, Shih-Che Kuo, Chia-Hung Chen. 1-2 [doi]
- ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip DesignSamuel Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, M. H. Yang, Kai-Chiang Wu. 1-7 [doi]
- Reconfigurable Database Processor for Query Acceleration on FPGABo-En Chen, Bo-Yen Lin, Bo-Cheng Lai. 1-4 [doi]
- Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance SystemsYu-sheng Lin, Wei-Chao Chen, Trista Pei-chun Chen. 1-3 [doi]
- Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFsSying-Jyan Wang, Tzu-Heng Chang, Katherine Shu-Min Li. 1-4 [doi]
- Opportunities for 2.5/3D Heterogeneous SoC IntegrationIris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen. 1 [doi]
- Self-Heating Effects from Transistors to GatesVictor M. van Santen, Linda Schillinger, Hussam Amrouch. 1-4 [doi]
- Shutdown mode implementation for Boost and Inverting Buck-Boost converterVenkatesh G. Kadlimatti, Sumit Bhat. 1-4 [doi]
- Learning Based Placement Refinement to Reduce DRC Short ViolationsYing-Yao Huang, Chang-Tzu Lin, Wei-Lun Liang, Hung-Ming Chen. 1-4 [doi]
- A Hybrid Supply Modulator for 10-MHz LTE Power Amplifier with 17.3% PAE ImprovementYen-Ting Chen, Mao-Ling Chiu, How-Wei Teng, Tsung-Hsien Lin. 1-2 [doi]
- An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction TechniqueBo-Wei Chen, Yung-Hui Chung, Chia-Ming Tsai. 1-4 [doi]
- A TinyMLaaS Ecosystem for Machine Learning in IoT: Overview and Research ChallengesHiroshi Doyu, Roberto Morabito, Martina Brachmann. 1-5 [doi]
- An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing TechniqueGuan-Yu Su, Zhi-Heng Kang, Shen-Iuan Liu. 1-4 [doi]
- Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON EventsHan-Sheng Huang, Ming-Dou Ker. 1-4 [doi]
- Machine Learning System-Enabled GPU Acceleration for EDATsung-Wei Huang. 1 [doi]
- Opportunity and Challenge of Chiplet-Based HPC and AIoTJie-Wei Lai. 1-2 [doi]
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-OptimizationM. D. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, Yarui Peng. 1-4 [doi]
- An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising MachinesSiya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa. 1-4 [doi]
- Gait Parameters Analysis Based on Leg-and-shoe-mounted IMU and Deep LearningPo-Hsin Lin, Chang-Lin Shih, Davy P. Y. Wong, Pai H. Chou. 1-4 [doi]
- Intelligence Everywhere: The Challenges and Opportunities for Semiconductor DesignsPin-Han Chen. 1-2 [doi]
- A 6.78MHz Wireless Power Transfer System with Maximum Power Tracking over Wide Load RangeYou-Xin Ling, Tsung-Heng Tsai. 1-4 [doi]
- A Test Method for Large-size TSV Considering Resistive Open Fault and Leakage Fault CoexistenceChang Hao, Xu Yong, Tianming Ni. 1-4 [doi]
- Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC PlatformKun-Chih Jimmy Chen, Chun-Chuan Wang, Cheng-Kang Tsai, Jing-Wen Liang. 1-4 [doi]
- 2 in 7nm FinFETMatthias Eberlein, Harald Pretl. 1-4 [doi]
- Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic BiochipsLing-Yen Song, Chih-Shen Yeh, Chien-Nan Liu, Juinn-Dar Huang. 1-4 [doi]