The following publications are possibly variants of this publication:
- An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructionsYuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. apccas 2002: 171-176 [doi]
- A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal ProcessingNozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki. aspdac 1999: 335-338 [doi]
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type InstructionsNozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki. ieiceta, 86-A(12):3099-3109, 2003. [doi]
- A hardware/software partitioning algorithm for SIMD processor coresKoichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki. aspdac 2003: 135-140 [doi]