D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011. pages 136-141, IEEE Computer Society, 2011. [doi]
@inproceedings{TranVBDGPW11,
title = {A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits},
author = {D. A. Tran and Arnaud Virazel and Alberto Bosio and Luigi Dilillo and Patrick Girard and Serge Pravossoudovitch and Hans-Joachim Wunderlich},
year = {2011},
doi = {10.1109/ATS.2011.89},
url = {http://doi.ieeecomputersociety.org/10.1109/ATS.2011.89},
researchr = {https://researchr.org/publication/TranVBDGPW11},
cites = {0},
citedby = {0},
pages = {136-141},
booktitle = {Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011},
publisher = {IEEE Computer Society},
isbn = {978-1-4577-1984-4},
}