Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq. Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. J. Solid-State Circuits, 55(7):1854-1863, 2020. [doi]

This author has not been identified. Look up 'Cheng-Hsueh Tsai' in GoogleThis author has not been identified. Look up 'Zhiwei Zong' in GoogleThis author has not been identified. Look up 'Federico Pepe' in GoogleThis author has not been identified. Look up 'Giovanni Mangraviti' in GoogleThis author has not been identified. Look up 'Jan Craninckx' in GoogleThis author has not been identified. Look up 'Piet Wambacq' in Google

runs on WebDSL