Shing-Wu Tung, Jing-Yang Jou. Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. In 7th Asian Test Symposium (ATS 98), 2-4 December 1998, Singapore. pages 402-407, IEEE Computer Society, 1998. [doi]
@inproceedings{TungJ98:0,
title = {Verification Pattern Generation for Core-Based Design Using Port Order Fault Model},
author = {Shing-Wu Tung and Jing-Yang Jou},
year = {1998},
url = {http://csdl.computer.org/comp/proceedings/ats/1998/8277/00/82770402abs.htm},
tags = {design},
researchr = {https://researchr.org/publication/TungJ98%3A0},
cites = {0},
citedby = {0},
pages = {402-407},
booktitle = {7th Asian Test Symposium (ATS 98), 2-4 December 1998, Singapore},
publisher = {IEEE Computer Society},
isbn = {0-8186-8277-9},
}