Verification Pattern Generation for Core-Based Design Using Port Order Fault Model

Shing-Wu Tung, Jing-Yang Jou. Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. In 7th Asian Test Symposium (ATS 98), 2-4 December 1998, Singapore. pages 402-407, IEEE Computer Society, 1998. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.