Energy minimization for hybrid BIST in a system-on-chip test environment

Raimund Ubar, Tatjana Shchenova, Gert Jervan, Zebo Peng. Energy minimization for hybrid BIST in a system-on-chip test environment. In 10th European Test Symposium (ETS 2005), May 22-25, 2005, Tallinn, Estonia. pages 2-7, IEEE, 2005. [doi]

@inproceedings{UbarSJP05,
  title = {Energy minimization for hybrid BIST in a system-on-chip test environment},
  author = {Raimund Ubar and Tatjana Shchenova and Gert Jervan and Zebo Peng},
  year = {2005},
  doi = {10.1109/ETS.2005.16},
  url = {http://doi.ieeecomputersociety.org/10.1109/ETS.2005.16},
  researchr = {https://researchr.org/publication/UbarSJP05},
  cites = {0},
  citedby = {0},
  pages = {2-7},
  booktitle = {10th European Test Symposium (ETS 2005), May 22-25, 2005, Tallinn, Estonia},
  publisher = {IEEE},
  isbn = {0-7695-2341-2},
}