Timing Error Tolerance in Small Core Designs for SoC Applications - researchr publication related

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Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Transactions on Computers, 65(2):654-663, 2016. [doi]

The following publications are possibly variants of this publication:

Timing Error Tolerance in Pipeline Based Core DesignsStefanos Valadimas, Angela Arapoyanni. pci 2014: 1-6 [doi]

Effective Timing Error Tolerance in Flip-Flop Based Core DesignsStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos. et, 29(6):795-804, 2013. [doi]

Timing error tolerance in nanometer ICsS. Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. iolts 2010: 283-288 [doi]

Cost and power efficient timing error tolerance in flip-flop based microprocessor coresStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. ets 2012: 1-6 [doi]

Timing error mitigation in microprocessor coresStefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas. icecsys 2016: 772-775 [doi]

The Time Dilation Technique for Timing Error ToleranceStefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos. TC, 63(5):1277-1286, 2014. [doi]

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