Fast FPGA-based pipelined digit-serial/parallel multipliers - researchr publication authors

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Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo. Fast FPGA-based pipelined digit-serial/parallel multipliers. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 482-485, IEEE, 1999. [doi]

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