Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo. Fast FPGA-based pipelined digit-serial/parallel multipliers. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 482-485, IEEE, 1999. [doi]
Abstract is missing.