Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo. Fast FPGA-based pipelined digit-serial/parallel multipliers. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 482-485, IEEE, 1999. [doi]
@inproceedings{VallsSPB99,
title = {Fast FPGA-based pipelined digit-serial/parallel multipliers},
author = {Javier Valls and T. Sansaloni and M. M. Peiro and Eduardo I. Boemo},
year = {1999},
doi = {10.1109/ISCAS.1999.777931},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.1999.777931},
tags = {rule-based},
researchr = {https://researchr.org/publication/VallsSPB99},
cites = {0},
citedby = {0},
pages = {482-485},
booktitle = {International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA},
publisher = {IEEE},
isbn = {0-7803-5471-0},
}