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Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Hugo Veenstra, G. A. M. Hurkx, Dave van Goor, Hans Brekelmans, John R. Long. Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/. J. Solid-State Circuits, 40(10):2008-2018, 2005. [doi]

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Hugo Veenstra

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G. A. M. Hurkx

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Dave van Goor

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Hans Brekelmans

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John R. Long

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