Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Hugo Veenstra, G. A. M. Hurkx, Dave van Goor, Hans Brekelmans, John R. Long. Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/. J. Solid-State Circuits, 40(10):2008-2018, 2005. [doi]

@article{VeenstraHGBL05,
  title = {Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/},
  author = {Hugo Veenstra and G. A. M. Hurkx and Dave van Goor and Hans Brekelmans and John R. Long},
  year = {2005},
  doi = {10.1109/JSSC.2005.852829},
  url = {https://doi.org/10.1109/JSSC.2005.852829},
  researchr = {https://researchr.org/publication/VeenstraHGBL05},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {40},
  number = {10},
  pages = {2008-2018},
}