Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/

Hugo Veenstra, G. A. M. Hurkx, Dave van Goor, Hans Brekelmans, John R. Long. Analyses and design of bias circuits tolerating output voltages above BV/sub CEO/. J. Solid-State Circuits, 40(10):2008-2018, 2005. [doi]

Abstract

Abstract is missing.