Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas. A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. J. Solid-State Circuits, 45(10):2080-2090, 2010. [doi]
@article{VerbruggenCKWP10,
title = {A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS},
author = {Bob Verbruggen and Jan Craninckx and Maarten Kuijk and Piet Wambacq and Geert Van der Plas},
year = {2010},
doi = {10.1109/JSSC.2010.2061611},
url = {http://dx.doi.org/10.1109/JSSC.2010.2061611},
researchr = {https://researchr.org/publication/VerbruggenCKWP10},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {45},
number = {10},
pages = {2080-2090},
}