Naveen Verma, Anantha P. Chandrakasan. A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 328-606, IEEE, 2007. [doi]
@inproceedings{VermaC07,
title = {A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy},
author = {Naveen Verma and Anantha P. Chandrakasan},
year = {2007},
doi = {10.1109/ISSCC.2007.373427},
url = {http://dx.doi.org/10.1109/ISSCC.2007.373427},
researchr = {https://researchr.org/publication/VermaC07},
cites = {0},
citedby = {0},
pages = {328-606},
booktitle = {2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007},
publisher = {IEEE},
isbn = {1-4244-0853-9},
}