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Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan. Online cache state dumping for processor debug. In Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009. pages 358-363, ACM, 2009. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Enhancing post-silicon processor debug with Incremental Cache state DumpingPreeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan. vlsi 2010: 55-60 [doi] Compressing Cache State for Postsilicon Processor DebugPreeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi. TC, 60(4):484-497, 2011. [doi] Cache aware compression for processor debug supportAnant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan. date 2009: 208-213 [doi]
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