Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh. Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. IEEE Trans. VLSI Syst., 28(9):2069-2073, 2020. [doi]

Abstract

Abstract is missing.