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Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh. Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. IEEE Trans. VLSI Syst., 28(9):2069-2073, 2020. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design of High-Performance CMOS Level Converters Considering PVT VariationsJinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh. ieicet, 94-C(5):913-916, 2011. [doi]
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