The following publications are possibly variants of this publication:
- 2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOSXiaoteng Zhao, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins. jssc, 57(2):546-561, 2022. [doi]
- A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition TechniqueLin Wang, Yong Chen 0005, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins. tcasI, 70(7):2637-2650, July 2023. [doi]
- 2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOSXiaoteng Zhao, Yong Chen 0005, Pui-In Mak, Rui P. Martins. cicc 2020: 1-4 [doi]