Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu. A BIST Scheme for FPGA Interconnect Delay Faults. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA. pages 201-206, IEEE Computer Society, 2005. [doi]
@inproceedings{WangLPHW05,
title = {A BIST Scheme for FPGA Interconnect Delay Faults},
author = {Chun-Chieh Wang and Jing-Jia Liou and Yen-Lin Peng and Chih-Tsun Huang and Cheng-Wen Wu},
year = {2005},
doi = {10.1109/VTS.2005.5},
url = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.5},
researchr = {https://researchr.org/publication/WangLPHW05},
cites = {0},
citedby = {0},
pages = {201-206},
booktitle = {23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-2314-5},
}