Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu. A BIST Scheme for FPGA Interconnect Delay Faults. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA. pages 201-206, IEEE Computer Society, 2005. [doi]
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