High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer - researchr publication authors

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Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu. High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. In 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013. pages 1-4, IEEE, 2013. [doi]

This author has not been identified. Look up 'Jiacheng Wang' in GoogleThis author has not been identified. Look up 'Shunli Ma' in GoogleThis author has not been identified. Look up 'Sai Manoj Pudukotai Dinakarrao' in GoogleThis author has not been identified. Look up 'Mingbin Yu' in GoogleThis author has not been identified. Look up 'Roshan Weerasekera' in GoogleThis author has not been identified. Look up 'Hao Yu' in Google

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