Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu. High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. In 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013. pages 1-4, IEEE, 2013. [doi]
@inproceedings{WangMDYWY13,
title = {High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer},
author = {Jiacheng Wang and Shunli Ma and Sai Manoj Pudukotai Dinakarrao and Mingbin Yu and Roshan Weerasekera and Hao Yu},
year = {2013},
doi = {10.1109/3DIC.2013.6702326},
url = {http://dx.doi.org/10.1109/3DIC.2013.6702326},
researchr = {https://researchr.org/publication/WangMDYWY13},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013},
publisher = {IEEE},
}