A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose. A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits, Devices & Systems, 17(2):75-87, March 2023. [doi]

@article{WangSTCLJ23,
  title = {A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process},
  author = {Chua-Chin Wang and Ralph Gerard B. Sangalang and I-Ting Tseng and Yi-Jen Chiu and Yu-Cheng Lin and Oliver Lexter July A. Jose},
  year = {2023},
  month = {March},
  doi = {10.1049/cds2.12141},
  url = {https://doi.org/10.1049/cds2.12141},
  researchr = {https://researchr.org/publication/WangSTCLJ23},
  cites = {0},
  citedby = {0},
  journal = {IET Circuits, Devices & Systems},
  volume = {17},
  number = {2},
  pages = {75-87},
}