The following publications are possibly variants of this publication:
- Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS TechnologyChua-Chin Wang, I-Ting Tseng. icicdt 2019: 1-4 [doi]
- A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS ProcessRalph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang. tcasII, 70(10):3862-3866, October 2023. [doi]
- 200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic ProcessChua-Chin Wang, Chien-Ping Kuo. tcasII, 68(9):3163-3166, 2021. [doi]
- A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS processChua-Chin Wang, Chiang-Hsiang Liao, Sih-Yu Chen. iscas 2014: 1126-1129 [doi]
- A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing MacroJiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang 0001, Runsheng Wang, Ru Huang. tcasI, 70(5):1835-1845, May 2023. [doi]
- Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS processSih-Yu Chen, Chua-Chin Wang. icicdt 2012: 1-4 [doi]