Table of Contents

• Evaluation of non-destructive etch depth measurement for through silicon viasThuy Dao, Tania Thomas, David Marx, David Grant. 1-4 [doi]
• O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compactionRani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta. 1-4 [doi]
• Gate delay modeling for static timing analysis of body-biased circuitsDonkyu Baek, Insup Shin, Youngsoo Shin. 1-4 [doi]
• Analytical modeling of parasitics in monolithically integrated 3D invertersJ. Lacord, P. Batude, Gérard Ghibaudo, Frédéric Boeuf. 1-4 [doi]
• Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reductionAtsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe. 1-4 [doi]
• Temperature and process compensated clock generator using feedback TPC biasTzung-Je Lee, Doron Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang. 1-4 [doi]
• First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memoriesJane Yater, S.-T. Kang, C. M. Hong, B. Min, D. Kolar, K. Loiko, J. Shen, B. Winstead, H. Gasquet, S. Mohammed, A. Hardell, W. Malloch, B. Cook, R. Syzdek, A. Jarrar, J. Feddeler, K. Baker, K. M. Chang, S. Herrin, R. Parks, G. Chindalore. 1-3 [doi]
• Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current sourceChia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang. 1-4 [doi]
• 3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumpsW. Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, M. Gonzalez, Yann Civale, A. Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, K. J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne, Bart Swinnen. 1-4 [doi]
• Design of low power, wider tuning range CMOS voltage control oscillator for ultra wideband applicationsAyobami B. Iji, Forest Zhu, Michael Heimlich. 1-4 [doi]
• Spatial variation decomposition via sparse regressionWangyang Zhang, Karthik Balakrishnan, Xin Li 0001, Duane S. Boning, Emrah Acar, Frank Liu, Rob A. Rutenbar. 1-4 [doi]
• Energy efficient design techniques for a digital signal processorPaul Bassett, Martin Saint-Laurent. 1-4 [doi]
• Design and analysis of IC power delivery with on-chip voltage regulationSuming Lai, Peng Li, Zhiyu Zeng. 1-4 [doi]
• Design driven patterning optimizations for low K1 lithographyKanak B. Agarwal, Shayak Banerjee. 1-4 [doi]
• Low-energy signal processing using circuit-level timing-error acceptanceKu He, Andreas Gerstlauer, Michael Orshansky. 1-4 [doi]
• Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyondBalaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer. 1-4 [doi]
• On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffersChih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang. 1-4 [doi]
• Using ECC and redundancy to minimize vmin induced yield loss in 6T SRAM arraysGururaj Shamanna, Raja Gaurav, Y. K. Raghavendra, Percy Marfatia, Bhunesh S. Kshatri. 1-4 [doi]
• Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS processSih-Yu Chen, Chua-Chin Wang. 1-4 [doi]
• High swing low capacitance ESD RF protections in advanced CMOS technologiesJean Jimenez, Philippe Galy, Johan Bourgeat, Boris Heitz. 1-4 [doi]
• A high voltage analog multiplexer with digital calibration for battery management systemsChih-Lin Chen, Yi Hu, Wayne Luo, Chua-Chin Wang, Chun-Ying Juan. 1-4 [doi]
• A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error toleranceSylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Dimitri Soussan, Philippe Roche. 1-4 [doi]
• Extending energy-saving voltage scaling in ultra low voltage integrated circuit designsMingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester. 1-4 [doi]
• 32 nm FinFET-based 0.7-to-1.1 V digital voltage sensor with 50 mV resolutionHung Viet Nguyen, Youngmin Kim. 1-4 [doi]
• Synthesis of clock gating logic through factored form matchingInhak Han, Youngsoo Shin. 1-4 [doi]
• A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixerRouhollah Feghhi, Sasan Naseh. 1-4 [doi]
• Variability in Fully Depleted MOSFETsMaud Vinet, T. Hook, Yannick Le Tiec, R. Murphy, Shom Ponoth, Laurent Grenouillet, Romain Wacquez. 1-3 [doi]
• BIMOS transistor and its applications in ESD protection in advanced CMOS technologyPhilippe Galy, Jean Jimenez, Johan Bourgeat, A. Dray, G. Troussier, Boris Heitz, Nicolas Guitard, D. Marin-Cudraz, H. Beckrich-Ros. 1-4 [doi]
• Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D worldC. Y. Kang, K. W. Ang, R. Hill, W. Y. Loh, J. Oh, R. Lee, David Gilmer, Gennadi Bersuker, C. Hobbs, Paul Kirsch, K. Hummler, S. Arkalgud, Raj Jammy. 1-4 [doi]
• A low power programmable FIR filter using sharing multiplication techniqueNahla T. Abou-El-Kheir, Moataz S. El-Kharashi, Magdy A. El-Moursy. 1-4 [doi]
• A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-BiasingDimitri Soussan, Alexandre Valentian, Sylvain Majcherczak, Marc Belleville. 1-4 [doi]
• System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI modelChenyun Pan, Azad Naeemi. 1-5 [doi]
• Lifetime prediction of channel hot carrier degradation in pMOSFETs separating NBTI componentYuichiro Mitani, Shigeto Fukatsu, D. Hagishima, K. Matsuzawa. 1-4 [doi]
• Low-power ultra-Wide-Band Impulse Radio transceivers for short range communicationsAndrea Neviani, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig. 1-4 [doi]
• Reliability driven guideline for BEOL Optimization: Protecting MOS stacks from hydrogen-related impurity penetrationZiyuan Liu, Fumihiko Hayashi, Shinji Fujieda, Markus Wilde, Katsuyuki Fukutani. 1-4 [doi]
• Optimization problems for plasma-induced damage - A concept for plasma-induced damage designKoji Eriguchi, Yoshinori Nakakubo, Asahiko Matsuda, Masayuki Kamei, Yoshinori Takao, Kouichi Ono. 1-4 [doi]
• "Phase-Change Memories for nano-scale technology and design"Fabio Pellizzer, Roberto Bez. 1-4 [doi]
• BAW filters for ultra-low power narrow-band applicationsCarolynn Bernier, J.-B. David. 1-4 [doi]
• A new statistical setup and hold time definitionXiaoliang Bai, Prayag Patel, Xiaonan Zhang. 1-4 [doi]
• Robust PEALD SiN spacer for gate first high-k metal gate integrationD. H. Triyoso, V. Jaschke, J. Shu, S. Mutas, K. Hempel, J. K. Schaeffer, M. Lenski. 1-4 [doi]
• Poly-Si Thin Film Transistors: Opportunities for low-cost RF applicationsSoo Youn Kim, Wing-Fai Loke, Sang Phill Park, Byunghoo Jung, Kaushik Roy. 1-4 [doi]
• Minimum logic of guaranteed single soft error resilience based on group distance-two codeBao Liu, Lu Wang. 1-4 [doi]
• System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistorsAhmet Ceyhan, Azad Naeemi. 1-4 [doi]
• Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applicationsJacopo Franco, Ben Kaczer, Jérôme Mitard, Maria Toledano-Luque, Felice Crupi, Geert Eneman, Ph. J. Rousse, Tibor Grasser, M. Cho, Thomas Kauerauf, Liesbeth Witters, Geert Hellings, L.-Å. Ragnarsson, Naoto Horiguchi, Marc M. Heyns, Guido Groeseneken. 1-4 [doi]
• Strained silicon on insulator substrates for fully depleted applicationW. Schwarzenbach, N. Daval, S. Kerdiles, G. Chabanne, C. Figuet, S. Guerroudj, O. Bonnin, X. Cauchy, B.-Y. Nguyen, C. Maleville. 1-4 [doi]
• 3D stacking: Where the rubber meets the roadChandra Nimmagadda, Durodami Lisk, Riko Radojcic. 1-3 [doi]
• Nanoscale power and heat management in electronicsAndrey Y. Serov, Zuanyi Li, Kyle L. Grosse, Albert D. Liao, David Estrada, Myung-Ho Bae, Feng Xiong, William P. King, Eric Pop. 1-5 [doi]
• Dynamic Stage Element Matching (DSEM) in Pipeline Analog to Digital Converters (ADC)Francis Fradette, Eric J. Balster, Frank A. Scarpino, Kerry L. Hill. 1-4 [doi]