The following publications are possibly variants of this publication:
- A 4-Kb low power 4-T SRAM design with negative word-line gate driveChua-Chin Wang, Ching-Li Lee, Wun-Ji Lin. iscas 2006: [doi]
- A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technologyChi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee. socc 2014: 160-164 [doi]
- 0.2 V 8T SRAM with improved bitline sensing using column-based data randomizationAnh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik Joon Chang, Tony Tae-Hyoung Kim. asscc 2014: 141-144 [doi]