A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

Can Wang, Guang Zhu, Zhao Zhang, C. Patrick Yue. A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 274, IEEE, 2019. [doi]

Authors

Can Wang

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Guang Zhu

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Zhao Zhang

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C. Patrick Yue

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